It is known in the art to employ a multiplicity of registers in a digital system. It is also known in the art to construct routes, in such a digital system for transferring data from one register to another register. A bus, which is an assemblage of common transmission lines controlled by switching circuits, has been utilized as a common route to efficiently perform data transmission between registers.
Recently, some bus architectures for embedded SOCs are changing to ones that basically are associated with at least one multiplexer (or MUX), i.e., MUX-based bus systems. Differences between the conventional tri-state bus systems and MUX-based bus systems architecture include such characteristics as ease for testing system performance. Automatic tools for electronic design, which establish test vectors, functionally tends to be more easily operable with the multiplexer-based buses rather than the tri-state buses. Furthermore, numerous electronic designs or designs tools are better suited for the MUX-based bus systems. In addition, it is more efficient to use MUX-based buses that are unidirectional, than other bus systems that are bi-directional, in order to enhance bus performance in chips.
However, many problems occur when the MUX-based buses are coupled to conventional MUX cells. Referring to FIG. 1, a conventional bus system associated with a multiplexer is depicted. A set of N signals is inputted into a centralized MUX 1. Each one of the N signals is composed of M bits. The set of N signals is applied to the centralized single MUX 1 from their respective data sources and then one of them is selected therefrom. This data source must provide all the interconnections that lead up to the MUX 1. Therefore, the total number of interconnections relating to the data source is M*N. For instance, when 32-bit buses are supplied from 11 data sources (a practical form in the design pattern of S3C2400X), all 352 (32*11) bits are involved in the MUX 1. Since a practical system employs numerous MUXs, the mutual interferences between the multiplicity of interconnections can cause increased signal delays.
Based upon usage and prior experiments, tri-state buses or wired-OR buses, which are used in large quantity in high-end processors, are regarded as insufficient for embedded systems such a SOC because of difficulties in testing.
As can be seen, there is a need for a bus system that is suitable for embedded systems with the bus system operating with relatively less interconnect. As well as a bus system that requires shortened interconnect lines.